Abstract: Google deployed several TPU generations since 2015, teaching us lessons that changed our views: semiconductor technology advances unequally; compiler compatibility trumps binary compatibility, especially for VLIW domain specific architectures; target total cost of ownership vs initial cost; support multi-tenancy; expect rapid deep neural network (DNN) growth; DNN advances evolve workloads; some inference tasks require floating point; and backwards ML compatibility helps deploy DNNs quickly and tunes them to the TPU. TPUv4i, deployed in 2020, was molded by these lessons.

Bio: David Patterson is a UC Berkeley professor, Google distinguished engineer, RISC-V International Vice-Chair, and RISC-V International Open Source Laboratory Director. His best known projects are RISC and RAID. He co-authored seven books, including Computer Architecture: A Quantitative Approach, and shared the 2017 ACM A.M Turing Award and the 2021 BBVA Foundation Frontiers of Knowledge Award with his co-author John Hennessy.